The present invention relates to a semiconductor read-only memory configuration having a semiconductor substrate and a to multiplicity of memory cells configured in a memory cell array in the semiconductor substrate. Each memory cell includes a plurality of transistors. The memory configuration includes word lines composed of polycrystalline silicon, and includes metal tracks, which run parallel to the word lines and which are isolated from the latter by an intermediate insulator. The word lines are ruptured in their longitudinal direction in each case after a first number of memory cells and can be refreshed via the metal tracks. A reference-ground potential can be applied to the semiconductor substrate via a substrate contact, in each case, after a second number of memory cells.
As is known, there are semiconductor read-only memory configurations with so-called diffusion read-only memories (ROMs) and so-called contact ROMs. In the case of diffusion ROMs, a diffusion is finally introduced in the entire memory cell array through a customized definition, while in the case of contact ROMs, the last step consists in providing the respective contacts in a manner corresponding to the customized definition. The diffusion involves the introduction of source zones and drain zones, while source contacts and drain contacts are created during the provision of the contacts.
In detail, in a memory cell array, the individual memory cells or the MOS field-effect transistors are completed except for the source and the drain diffusion or except for the source and the drain contacts. In accordance with the memory content to be stored in the read-only memory configuration, the individual transistors are then provided with the source and the drain diffusion or with the source and the drain contacts. In this case, a transistor with diffusion (or contacts) signifies a logic xe2x80x9c0xe2x80x9d, while a transistor without diffusion (or without contacts) is assigned a logic xe2x80x9c1xe2x80x9d. In other words, if a transistor is present, then this means a logic xe2x80x9c0xe2x80x9d, while the absence of a transistor through the absence of diffusion or contacts is assigned to a logic xe2x80x9c1xe2x80x9d.
In the memory cell array of such a semiconductor read-only memory configuration, it is necessary, then, to effect a well contact connection, a so-called rupture of the word line and a metal/polysilicon bridge. In the case of the well contact connection, a so-called substrate contact applies the reference-ground potential Vss to the well zone of the memory cells, while the word line is ruptured, since the polycrystalline silicon forming the word line must be interrupted after specific lengths for capacitance reasons or according to the so-called xe2x80x9cESD (Electrostatic Discharge) rulesxe2x80x9d. Moreover, it is necessary for the signals impressed on the polycrystalline silicon of the word lines likewise to be refreshed after a specific length. This is done, then, as follows: after a technology-dependent x-fold, for example 100-fold, width of a transistor via which a word line is led, the polycrystalline silicon thereof is interrupted and the word line is refreshed by a metal/polysilicon bridge. For this metal/polysilicon bridge, a metal track made, for example, of aluminum or copper runs above the polycrystalline silicon of the word line, and is isolated from the latter by an intermediate insulator made, for example, of silicon dioxide. In order to refresh a signal that is transferred by the polycrystalline silicon of the word line, a connection is established between the metal track and the polycrystalline silicon.
If it is assumed that, by way of example, eight transistors arranged in two rows form a memory cell, then after a first number of memory cells, for example three memory cells, a substrate contact is provided, while a rupture of the word line or of the refresh thereof is in each case performed after a second number of memory cells, for example, nine memory cells.
The well contact connection with the substrate contacts and also rupture and refresh of the word line thus do not take place in the memory cells of the memory cell array, but rather at regular intervals along the individual word lines. This inevitably necessitates further intermediate cells. In each case, after a first number of memory cells, an intermediate cell is provided for a substrate contact for the well contact connection, while rupture and refresh of the word line are effected, in each case, after a second number of memory cells.
FIG. 3 shows a plan view of a conventional semiconductor read-only memory configuration having memory cell arrays 1 to 3, which each include memory cells having 4xc3x972 transistors. After every three memory cells (in this respect cf. an upper row 4 of these memory cells), an intermediate cell 5 is present with a substrate contact via which reference-ground potential Vss is applied to the well of the memory cell arrays 1 to 3. At an interval of every nine memory cells, there is a rupture and a refresh of the word lines WL is performed at intermediate cells 6. Here, the polycrystalline silicon of the word lines is interrupted, and in each case, is connected by the overlying intermediate insulator to the metal track that is guided thereon.
Thus, in the case of the existing semiconductor read-only memory configuration, a relatively large amount of space is required for the intermediate cells, as can be seen from the plan view of FIG. 3.
FIG. 4 shows one of the intermediate cells 5 on an enlarged scale. A metal layer or track 7 is arranged above a word line WL made of polycrystalline silicon, is isolated from the latter by an intermediate insulator, and runs parallel to the polycrystalline silicon of the word line WL. A metalization layer 8 is provided above this metal track 7, which is likewise isolated from the metal track 7 by an intermediate insulator. This metalization layer 8 feeds reference-ground potential Vss, via a substrate contact 9, to the well of the memory cell arrays.
FIG. 5 shows an intermediate cell 6 with an interruption or a rupture 10 of the polycrystalline silicon of the word line WL. A plated-through hole 11 is provided between the respective metal track 7 and the polycrystalline silicon of the underlying word line WL, and a substrate contact 12 is provided.
To summarize, then, it must be emphasized that two different intermediate cells are required in existing semiconductor read-only memory configurations. The first intermediate cells serve for well contact connection, while rupture, refresh and well contact connection of the polycrystalline silicon of the word lines are performed in the second intermediate cells. Overall, this requires that the two intermediate cells occur frequently, which necessarily entails a reduction in the number of actual memory cells between the intermediate cells. Ultimately, this means that memory space is lost in the semiconductor read-only memory configuration, which is a critical obstacle to further miniaturization of the configuration.
It is accordingly an object of the invention to provide a semiconductor read-only memory configuration which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide a semiconductor read-only memory configuration which requires less space through the use of fewer intermediate cells for substrate contacts, rupture and refresh, and thus allows the area that is available for the actual memory cells to be enlarged.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor read-only memory configuration, that includes: a semiconductor substrate; a memory cell array located in the semiconductor substrate; a plurality of memory cells configured in the memory cell array, each one of the plurality of memory cells including a plurality of transistors; word lines made of polycrystalline silicon, the word lines running in a longitudinal direction, the word lines formed with ruptures located in the longitudinal direction after a first number of the plurality of the memory cells; metal tracks running parallel to the word lines for refreshing the word lines; an intermediate insulator isolating the word lines from the metal tracks; a plurality of substrate contacts, each one of the plurality of the substrate contacts located after a second number of the plurality of the memory cells for applying a reference-ground potential to the semiconductor substrate; and a plurality of intermediate cells periodically located in the longitudinal direction. Each one of the plurality of the intermediate cells includes a first intermediated cell half and a second intermediate cell half that are directly adjacent to one another perpendicularly to the longitudinal direction and that are alternately interchanged. The first intermediate cell half affects a respective one of the ruptures of a respective one of the word lines and includes a respective one of the plurality of the substrate contacts. The second intermediate cell half refreshes the polycrystalline silicon of the respective one of the word lines.
In the case of the semiconductor read-only memory configuration of the type mentioned in the introduction, this object is achieved by providing two intermediate cell halves that are directly adjacent to one another perpendicularly to the longitudinal direction of the word line and that are periodically repeated in the longitudinal direction of the word line. In a first intermediate cell half, the polycrystalline silicon of the word lines is ruptured and a substrate contact is set, and in a second intermediate cell half, the polycrystalline silicon is refreshed. These intermediate cell halves are adjacent to one another, and the first and the second intermediate cell halves are alternately interchanged.
Instead of two intermediate cells, the invention requires just one intermediate cell including two intermediate cell halves which are used in an alternately mirrored manner.
For example, consider the case when two memory cells lie one above the other and include a total of 4xc3x974 transistors, then in the intermediate cell half for the upper memory cell including 4xc3x972 transistors, the polycrystalline silicon is ruptured and the well contact connection is performed with the aid of a substrate contact. In the lower intermediate cell, half for the lower memory cells that likewise include 4xc3x972 transistors, the word line is refreshed by bridging the metal track to the polycrystalline silicon by means of contacts made of tungsten. This intermediate cell is used alternately, so that in each case one of the two rows of upper and lower memory cells is sometimes interrupted and sometimes refreshed.
The configuration of the intermediate cells that extends over two rows of memory cells enables a space saving in the order of magnitude of 42 to 47%, since only one type of intermediate cell is required, which is used in an alternately mirrored manner. The use of only one type of intermediate cell results, moreover, in a simplified construction of the semiconductor read-only memory configuration.
In accordance with an added feature of the invention, the semiconductor read-only memory configuration can readily be used with memory cells which have diffusion ROMs or contact ROMs. Furthermore, in the configuration, a well contact connection takes place with the same frequency as a rupture or a refresh of the polycrystalline silicon of the word lines.
In accordance with a concomitant feature of the invention, the individual contacts for well contact connection, that is to say the substrate contacts, and also the plated-through holes for the refresh lie in a row perpendicularly to the longitudinal direction of the word lines, so that the intermediate cell constructed in this way requires a particularly small amount of space. By virtue of the intermediate cell height extending over two memory cells, that is to say overall an xe2x80x9ceven-numberedxe2x80x9d cell height of the intermediate cell, the design of the semiconductor read-only memory configuration is facilitated since the intermediate cell is extended over two rows of memory cells.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in Semiconductor read-only memory configuration with substrate contacts and polysilicon bridge cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.